US 12,381,111 B2
Wafer bonding method and bonded wafer
Chao Wang, Wuhan (CN); Youdong Jiang, Wuhan (CN); Yulong Zhang, Wuhan (CN); and Zhiyong Suo, Wuhan (CN)
Assigned to Yangtze Memory Technologies Co., Ltd., Hubei (CN)
Filed by Yangtze Memory Technologies Co., Ltd., Wuhan (CN)
Filed on Dec. 14, 2021, as Appl. No. 17/644,135.
Claims priority of application No. 202011471584.2 (CN), filed on Dec. 14, 2020.
Prior Publication US 2022/0189822 A1, Jun. 16, 2022
Int. Cl. H01L 21/768 (2006.01); H01L 23/00 (2006.01); H01L 23/538 (2006.01)
CPC H01L 21/76802 (2013.01) [H01L 21/76843 (2013.01); H01L 21/76877 (2013.01); H01L 23/5384 (2013.01); H01L 23/5386 (2013.01); H01L 24/82 (2013.01); H01L 2224/82896 (2013.01)] 7 Claims
OG exemplary drawing
 
1. A bonded wafer, comprising:
a first semiconductor structure, including a first substrate, a first insulation layer disposed over the first substrate, a first conductive element disposed in the first insulation layer, and a first connection layer covering the first conductive element;
a second semiconductor structure, including a second substrate, a second insulation layer disposed over the second substrate, a second conductive element disposed in the second insulation layer, and a second connection layer covering the second conductive element; and
a first grain fusion layer, including a crystal grain fusion of at least a portion of the first connection layer and at least a portion of the second connection layer, wherein the first connection layer is made of a first connection material having a grain size smaller than a first conductive material of the first conductive element.