| CPC H01L 21/0274 (2013.01) [H01L 21/308 (2013.01); H10D 30/024 (2025.01); H10D 30/62 (2025.01); H10D 84/0158 (2025.01); H10D 84/038 (2025.01)] | 20 Claims |
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1. A method comprising:
forming over a substrate a transistor comprising a gate structure and respective source/drain features on respective sides of the gate structure;
forming over the transistor a conductive element in electrical communication with the transistor, the conductive element being embedded within a first dielectric layer;
depositing over the conductive element and the first dielectric layer an etch stop layer;
depositing over the etch stop layer a second dielectric layer;
forming a mask on the second dielectric layer;
patterning the mask to form a hole in the mask;
while the mask remains at least partially over the second dielectric layer, extending the hole to extend through the second dielectric layer using a first etch process;
while the mask remains at least partially over the second dielectric layer, extending the hole to extend through the etch stop layer using a second etch process; and
filling the hole with a contact plug that is electrically connected to the conductive element.
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10. A method comprising:
forming a conductive element surrounded by a first dielectric layer;
depositing an etch stop layer over the first dielectric layer;
depositing a second dielectric layer over the first dielectric layer;
forming a multi-layer mask;
patterning an opening into a first layer of the multi-layer mask using a photo lithography process;
using the first layer of the multi-layer mask as an etch mask, patterning a second layer of the multi-layer mask with a first etch process to include the opening, wherein the first layer of the multi-layer mask is at least partially consumed by the first etch process; and
using the second layer of the multi-layer mask as an etch mask, patterning the second dielectric layer with a second etch process to include the opening, and patterning the etch stop layer with a third separate etch process to include the opening, whereby the opening exposes the conductive element after the second etch process.
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15. A method comprising:
forming over a substrate a transistor comprising a gate structure, respective source/drain features on respective sides of the gate structure, and respective source/drain contacts on respective source/drain features;
recessing a portion of the gate structure to form a recess, and filling the recess with a dielectric gate cap;
depositing over the transistor an etch stop layer;
depositing over the etch stop layer a dielectric layer;
forming a mask over the dielectric layer;
patterning the mask to form a hole in the mask;
while at least a portion of the mask remains in place, extending the hole through the dielectric layer, the etch stop layer, and the dielectric gate cap to expo se a portion of the transistor; and
forming a transistor contact in the hole.
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