US 12,380,961 B2
Control method, semiconductor memory, and electronic device
Yoonjoo Eom, Hefei (CN); Lin Wang, Hefei (CN); Zhiqiang Zhang, Hefei (CN); and Yuanyuan Gong, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on Jan. 17, 2023, as Appl. No. 18/155,632.
Application 18/155,632 is a continuation of application No. PCT/CN2022/094333, filed on May 23, 2022.
Claims priority of application No. 202210307306.6 (CN), filed on Mar. 25, 2022.
Prior Publication US 2023/0307082 A1, Sep. 28, 2023
Int. Cl. G11C 29/46 (2006.01); G11C 29/12 (2006.01); G11C 29/38 (2006.01)
CPC G11C 29/46 (2013.01) [G11C 29/1201 (2013.01); G11C 29/38 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A control method, applied to a semiconductor memory, the semiconductor memory comprising a Data Mask (DM) pin, wherein the DM pin is used for receiving an input mask signal, the input mask signal is a signal for controlling writing data into the semiconductor memory, and the method comprises:
in response to that the semiconductor memory is in a preset test mode,
when a fourth Operand (OP) in a first Model Register (MR) indicates to enable the DM pin, controlling an impedance of the DM pin to be a first impedance parameter or a second impedance parameter according to a third OP in a third MR, wherein the third OP indicates whether the DM pin is to be tested in the preset test mode; or
when the fourth OP in the first MR indicates not to enable the DM pin, controlling the impedance of the DM pin to be in a high impedance state.