US 12,380,956 B2
Multi-state one-time programmable memory circuit
Chen-Feng Chang, Taoyuan (TW); Yu-Chen Lo, Taipei (TW); Tsung-Han Lu, New Taipei (TW); Shu-Chieh Chang, Taoyuan (TW); Chun-Hao Liang, New Taipei (TW); Dong-Yu Wu, Taipei (TW); and Meng-Lin Wu, Taoyuan (TW)
Assigned to Jmem Technology Co., Ltd., Taipei (TW)
Filed by Jmem Technology Co., Ltd., Taipei (TW)
Filed on Aug. 22, 2023, as Appl. No. 18/236,915.
Claims priority of provisional application 63/370,690, filed on Oct. 20, 2022.
Claims priority of provisional application 63/373,383, filed on Aug. 24, 2022.
Prior Publication US 2024/0071538 A1, Feb. 29, 2024
Int. Cl. G11C 17/16 (2006.01); G11C 17/18 (2006.01)
CPC G11C 17/165 (2013.01) [G11C 17/18 (2013.01)] 22 Claims
OG exemplary drawing
 
1. A multi-state one-time programmable (MSOTP) memory circuit comprising:
a first bit line and a second bit line;
a first word line and a second word line;
a memory cell including:
a metal oxide semiconductor field effect (MOS) storage transistor having a gate, a first electrode and a second electrode, wherein a first non-breakdown state or a first breakdown state exists between the gate and the first electrode of MOS storage transistor, and a second non-breakdown state or a second breakdown state exists between the gate and the second electrode of MOS storage transistor;
a first metal oxide semiconductor field effect (MOS) access transistor having a first gate, a first electrode and a second electrode, wherein the first gate is electrically connected to the first word line, the first electrode of the first MOS access transistor is electrically connected to the first bit line, and the second electrode of the first MOS access transistor is electrically connected to the first electrode of the MOS storage transistor; and
a second metal oxide semiconductor field effect (MOS) access transistor having a second gate, a first electrode and a second electrode, wherein the second gate is electrically connected to the second word line, the first electrode of the second MOS access transistor is electrically connected to the second electrode of the MOS storage transistor, and the second electrode of the second MOS access transistor is electrically connected to the second bit line; and
a programming voltage driving circuit electrically connected to the gate of the MOS storage transistor and configured to selectively output one of a writing control potential and a reading control potential, wherein:
the programming voltage driving circuit outputs the writing control potential to the gate of the MOS storage transistor when the memory cell is in a first writing state; and
the programming voltage driving circuit outputs the reading control potential to the gate of the MOS storage transistor when the memory cell is in a reading state.