US 12,380,954 B2
Dynamic 1-tier scan for high performance 3D NAND
Xiang Yang, Santa Clara, CA (US); Deepanshu Dutta, Fremont, CA (US); and Huai-yuan Tseng, San Ramon, CA (US)
Assigned to Sandisk Technologies, Inc., Milpitas, CA (US)
Filed by SanDisk Technologies LLC, Addison, TX (US)
Filed on Jun. 24, 2020, as Appl. No. 16/910,543.
Application 16/910,543 is a continuation of application No. 16/430,851, filed on Jun. 4, 2019, granted, now 10,714,198.
Prior Publication US 2020/0388343 A1, Dec. 10, 2020
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 16/34 (2006.01); G11C 11/56 (2006.01); G11C 16/08 (2006.01); G11C 16/10 (2006.01)
CPC G11C 16/3459 (2013.01) [G11C 11/5628 (2013.01); G11C 16/08 (2013.01); G11C 16/10 (2013.01)] 13 Claims
OG exemplary drawing
 
1. A non-volatile memory storage system comprising:
a memory block including string groups of memory holes that are separated from one another by trenches;
a NAND memory cell array comprising a plurality of memory cells that are being programmed to a first data state of a plurality of data states and are organized based on their locations within the memory block relative to the trenches into a plurality of distinct sub-groups including a first sub-group and a second sub-group with the memory cells of the first sub-group being located adjacent to the trenches and the memory cells of the second sub-group being spaced from the trenches such that the memory cells of the first sub-group are between the trenches and the memory cells of the second sub-group;
a dynamic 1-tier circuit configured to execute a first program loop and a second program loop;
wherein the first program loop comprises:
the dynamic 1-tier circuit applying at least one programming pulse to program the memory cells of both of the first and second sub-groups simultaneously, verifying only the memory cells of the first sub-group, comparing a number of memory cells of the first sub-group that have achieved a verify level to a first sub-group numeric threshold,
if the first sub-group numeric threshold is not met, the dynamic 1-tier circuit increasing a voltage of the programming pulses and repeating the first program loop, and
if the first sub-group numeric threshold is met, the dynamic 1-tier circuit executing the second program loop, wherein the second program loop comprises:
the dynamic 1-tier circuit verifying only the memory cells of the second sub-group and comparing a number of memory cells of the second sub-group that have achieved the verify level to a second sub-group numeric threshold, and
if the second sub-group numeric threshold is not met, the dynamic 1-tier circuit increasing the voltage of the programming pulses and applying one or more programming pulses to the first and second sub-groups and repeating the second program loop.