US 12,380,945 B2
Memory device with word line pulse recovery
Wei-jer Hsieh, Hsinchu (TW); Yu-Hao Hsu, Tainan (TW); Zhi-Hao Chang, Hsinchu (TW); and Cheng Hung Lee, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jan. 19, 2024, as Appl. No. 18/417,325.
Application 18/417,325 is a continuation of application No. 17/743,073, filed on May 12, 2022, granted, now 11,915,746.
Application 17/743,073 is a continuation of application No. 17/002,473, filed on Aug. 25, 2020, granted, now 11,355,183, issued on Jun. 7, 2022.
Prior Publication US 2024/0161822 A1, May 16, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 11/419 (2006.01)
CPC G11C 11/419 (2013.01) 20 Claims
OG exemplary drawing
 
1. A method of operating a memory device, comprising:
transitioning, from a first logic state to a second logic state, a word line (WL) coupled to a memory cell;
coupling a tracking WL to at least one of a bit line (BL) coupled to the memory cell or a first tracking BL emulating the BL, wherein the tracking WL emulates the WL with a decreased slope during a rising edge when transitioning from the first logic state to the second logic state responsive to the coupling; and
discharging a second tracking BL emulating the BL according to the decreased slope.