US 12,380,938 B2
Memory device, semiconductor device, and electronic device
Yuto Yakubo, Kanagawa (JP); and Takahiko Ishizu, Kanagawa (JP)
Assigned to Semiconductor Energy Laboratory Co., Ltd., Kanagawa-ken (JP)
Filed by SEMICONDUCTOR ENERGY LABORATORY CO., LTD., Atsugi (JP)
Filed on Jan. 10, 2024, as Appl. No. 18/409,150.
Application 18/409,150 is a continuation of application No. 17/625,922, granted, now 11,875,838, previously published as PCT/IB2020/056325, filed on Jul. 6, 2020.
Claims priority of application No. 2019-130021 (JP), filed on Jul. 12, 2019.
Prior Publication US 2024/0221812 A1, Jul. 4, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 11/405 (2006.01); G11C 11/4096 (2006.01); H10B 12/00 (2023.01); H10D 30/67 (2025.01); H10D 86/40 (2025.01); H10D 86/60 (2025.01)
CPC G11C 11/405 (2013.01) [G11C 11/4096 (2013.01); H10B 12/00 (2023.02); H10D 30/6734 (2025.01); H10D 30/6755 (2025.01); H10D 86/423 (2025.01); H10D 86/441 (2025.01); H10D 86/481 (2025.01); H10D 86/60 (2025.01)] 15 Claims
OG exemplary drawing
 
1. A memory device comprising:
a memory cell array comprising a first memory cell and a second memory cell;
a reading circuit electrically connected to the memory cell array; and
a processor electrically connected to the memory cell array and the reading circuit,
wherein each of the reading circuit and the processor comprises a transistor comprising silicon in a channel formation region,
wherein each of the first memory cell and the second memory cell comprise a transistor comprising a metal oxide in a channel formation region,
wherein the first memory cell is electrically connected to the reading circuit through a first wiring,
wherein the second memory cell is electrically connected to the reading circuit through a second wiring,
wherein the first wiring is configured to flow a first current corresponding to first data retained in the first memory cell from the reading circuit to the first memory cell,
wherein the second wiring is configured to flow a second current corresponding to second data retained in the second memory cell from the reading circuit to the second memory cell, and
wherein the reading circuit is configured to compare the first current and the second current and output a voltage corresponding to data read from the first memory cell.