US 12,380,933 B2
Pseudo-static random access memory
Hitoshi Ikeda, Yokohama (JP); and Takahiko Sato, Yokohama (JP)
Assigned to WINDBOND ELECTRONICS CORP., Taichung (TW)
Filed by Winbond Electronics Corp., Taichung (TW)
Filed on Oct. 5, 2022, as Appl. No. 17/960,433.
Claims priority of application No. 2021-181689 (JP), filed on Nov. 8, 2021.
Prior Publication US 2023/0143405 A1, May 11, 2023
Int. Cl. G11C 7/10 (2006.01)
CPC G11C 7/1093 (2013.01) [G11C 7/1048 (2013.01); G11C 7/1063 (2013.01)] 12 Claims
OG exemplary drawing
 
1. A pseudo-static random access memory inputting or outputting data to/from memory cells corresponding to a row address and a column address that are input in a first operation after an initial delay starting from a moment that a command and the row address are input, comprising:
a control unit, controlling a delay in a second operation less than the initial delay when a specific condition is satisfied, wherein the second operation is executed after the first operation.