	US 12,380,932 B2
	Row decoder and row address scheme in a memory system
Kha Nguyen, Ho Chi Minh (VN); Anh Ly, San Jose, CA (US); Hieu Van Tran, San Jose, CA (US); Hien Pham, Ho Chi Minh (VN); and Henry Tran, Ho Chi Minh (VN)
Assigned to Silicon Storage Technology, Inc., San Jose, CA (US)
Filed by Silicon Storage Technology, Inc., San Jose, CA (US)
Filed on Jun. 6, 2023, as Appl. No. 18/206,488.
Claims priority of provisional application 63/457,751, filed on Apr. 6, 2023.
Prior Publication US 2024/0339136 A1, Oct. 10, 2024
Int. Cl. G11C 7/10 (2006.01); G11C 7/12 (2006.01)

CPC G11C 7/1039 (2013.01) [G11C 7/12 (2013.01)]

20 Claims

1. A memory system comprising:

m banks of non-volatile memory cells, the m banks respectively comprising n or fewer sectors and the sectors respectively comprising p rows; and

a row decoder to receive a row address comprising r bits and to identify (i) a row using the least significant t bits in the r bits, (ii) a bank using the next u least significant bits, and (iii) a sector using the next v least significant bits, where m≤2^u, n≤2^v, and p≤2^t.