US 12,380,930 B2
Memory array decoding and interconnects
Hernan A. Castro, Shingle Springs, CA (US); Stephen W. Russell, Boise, ID (US); and Stephen H. Tang, Fremont, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Nov. 30, 2023, as Appl. No. 18/525,136.
Application 18/525,136 is a division of application No. 17/970,759, filed on Oct. 21, 2022, granted, now 11,862,280.
Application 17/970,759 is a division of application No. 17/062,024, filed on Oct. 2, 2020, granted, now 11,501,803, issued on Nov. 15, 2022.
Application 17/062,024 is a division of application No. 16/223,632, filed on Dec. 18, 2018, granted, now 10,818,324, issued on Oct. 27, 2020.
Prior Publication US 2024/0185892 A1, Jun. 6, 2024
Int. Cl. G11C 5/06 (2006.01); G11C 8/10 (2006.01); H01L 23/50 (2006.01)
CPC G11C 5/06 (2013.01) [G11C 8/10 (2013.01); H01L 23/50 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
receiving an indication of an access operation for a memory cell;
identifying a first deck of memory cells that includes the memory cell, the first deck included in a plurality of decks;
coupling, based at least in part on the identifying and using a first transistor included in the first deck, a first electrode included in the first deck with a first conductive plug that extends through the plurality of decks, wherein the first transistor comprises a gate electrode and a semiconductor material at least partially surrounding the gate electrode; and
driving, based at least in part on coupling the first electrode with the first conductive plug and with the semiconductor material of the first transistor, the first electrode to a voltage associated with the access operation.