US 12,380,826 B2
Spatial dithering technology that supports display scan-out
Susanta Bhattacharjee, Bangalore (IN); and Gary Smith, Northstowe (GB)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jun. 23, 2021, as Appl. No. 17/344,599.
Prior Publication US 2022/0415234 A1, Dec. 29, 2022
Int. Cl. G06F 7/58 (2006.01); G09G 3/20 (2006.01); G09G 5/02 (2006.01); H04N 19/00 (2014.01)
CPC G09G 3/2003 (2013.01) [G09G 5/026 (2013.01); G09G 2310/0267 (2013.01)] 32 Claims
OG exemplary drawing
 
1. A computing system comprising:
a display panel; and
a display controller including logic coupled to one or more substrates, wherein the logic is to:
generate a seed value based solely on coordinates for a position of an input pixel such that the seed value is dedicated to the position of the input pixel,
generate a dithered pixel value based on the seed value and a value of the input pixel, and
conduct a scan-out of the dithered pixel value to the display panel.