US 12,380,325 B2
Neural processing device and method for synchronization thereof
Jinwook Oh, Seongnam-si (KR); Jinseok Kim, Seongnam-si (KR); Kyeongryeol Bong, Seongnam-si (KR); Wongyu Shin, Seongnam-si (KR); and Chang-Hyo Yu, Seongnam-si (KR)
Assigned to Rebellions Inc., Seongnam-si (KR)
Filed by Rebellions Inc., Seongnam-si (KR)
Filed on Apr. 11, 2023, as Appl. No. 18/298,935.
Application 18/298,935 is a continuation of application No. 17/661,414, filed on Apr. 29, 2022, granted, now 11,657,261.
Claims priority of application No. 10-2021-0192179 (KR), filed on Dec. 30, 2021.
Prior Publication US 2023/0244920 A1, Aug. 3, 2023
Int. Cl. G06N 3/063 (2023.01); G06F 5/06 (2006.01); G06F 9/38 (2018.01); G06F 9/52 (2006.01)
CPC G06N 3/063 (2013.01) [G06F 5/065 (2013.01); G06F 9/3877 (2013.01); G06F 9/52 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A neural processing device comprising:
first and second neural cores; and,
an L2 sync path configured to directly transmit an L2 synchronization signal between the first and second neural cores,
wherein the first neural core comprises,
a first local memory included in the first neural core and temporarily storing first data to be input and output,
a first load/store unit (LSU) included in the first neural core and moving the first data in the first local memory,
a processing unit included in the first neural core and performing an computation operation on the first data,
a data path through which the first data is transmitted between the local memory, the first LSU, and the processing unit, and
an L1 sync path configured to transmit an L1 synchronization signal, in the first neural core, between the first local memory, the first LSU, and the processing unit, wherein the L1 sync path is a separate path from the data path.