| CPC G06K 7/1443 (2013.01) [G06T 7/11 (2017.01); G06V 10/25 (2022.01); G06V 10/751 (2022.01); G06V 10/764 (2022.01)] | 20 Claims |
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1. An apparatus comprising:
at least one processor; and
a memory operably connected to the at least one processor, wherein the memory stores instructions for causing the at least one processor to perform operations in response to execution of the instructions by the at least one processor, the operations comprising:
obtaining a marker image including a coded marker from an input image and normalizing the marker image to obtain a normalized image;
detecting a region of interest in the normalized image;
generating a first binarized image by performing binarization to classify each pixel of the normalized image into one of a foreground and a background;
generating a second binarized image by dividing the normalized image into a plurality of partitions, performing binarization for pixel values for each partition to generate a binarized image for the each partition, and combining the binarized images for the each partition;
generating an integrated binarized image according to a result of comparing pixel values at a same location in the first binarized image and the second binarized image; and
obtaining identification data of the coded marker from the integrated binarized image.
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