US 12,380,266 B2
Layout design method and method of manufacturing integrated circuit device using the same
Dawoon Choi, Suwon-si (KR); Inseop Lee, Suwon-si (KR); Hee Jeong, Suwon-si (KR); Bongkeun Kim, Suwon-si (KR); and Myungsoo Noh, Suwon-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Sep. 21, 2023, as Appl. No. 18/370,921.
Claims priority of application No. 10-2022-0120169 (KR), filed on Sep. 22, 2022.
Prior Publication US 2024/0104287 A1, Mar. 28, 2024
Int. Cl. G06F 30/398 (2020.01); G03F 1/36 (2012.01); G06F 30/392 (2020.01)
CPC G06F 30/398 (2020.01) [G03F 1/36 (2013.01); G06F 30/392 (2020.01)] 20 Claims
OG exemplary drawing
 
1. A layout design method comprising:
designing a preliminary layout including a source/drain contact pattern of an integrated circuit device;
designing a first layout including a cut pattern for cutting the source/drain contact pattern;
designing a second layout including a pattern configured by excluding a pattern overlapping the cut pattern of the first layout from the preliminary layout; and
correcting the preliminary layout by reflecting an etch skew based on at least one parameter of the second layout.