US 12,380,263 B2
Method for viewing simulation signals of digital products and simulation system
Kaipeng Lin, Guangdong (CN); Yanrong Li, Guangdong (CN); and Xiaoli Huang, Guangdong (CN)
Assigned to SHENZHEN GUOWEIXIN TECHNOLOGY CO., LTD, Guangdong (CN)
Appl. No. 17/792,480
Filed by SHENZHEN GUOWEIXIN TECHNOLOGY CO., LTD, Shenzhen (CN)
PCT Filed Mar. 25, 2020, PCT No. PCT/CN2020/081215
§ 371(c)(1), (2) Date Jul. 13, 2022,
PCT Pub. No. WO2021/109365, PCT Pub. Date Jun. 10, 2021.
Claims priority of application No. 201911244649.7 (CN), filed on Dec. 6, 2019.
Prior Publication US 2023/0057034 A1, Feb. 23, 2023
Int. Cl. G06F 30/343 (2020.01); G06F 9/455 (2018.01); G06F 11/07 (2006.01); G06F 30/3308 (2020.01); G06F 30/331 (2020.01); G06F 30/3323 (2020.01); G06F 30/34 (2020.01); G06F 30/367 (2020.01); G06F 30/398 (2020.01)
CPC G06F 30/343 (2020.01) [G06F 30/3308 (2020.01); G06F 30/3323 (2020.01); G06F 9/455 (2013.01); G06F 11/07 (2013.01); G06F 30/331 (2020.01); G06F 30/34 (2020.01); G06F 30/367 (2020.01); G06F 30/398 (2020.01)] 5 Claims
OG exemplary drawing
 
1. A method for viewing simulation signals of digital products, comprising:
when performing FPGA simulation on said digital products, reading out all external port status data of said digital products in real time by adopting a dynamic probe detection method and recording the external port status data being read out in real time as simulation data, and reading out all internal status data of said digital products once every interval time by adopting a static probe detection method and recording the internal status data being read out once every interval time as part of the simulation data;
after completing the FPGA simulation, when needing a back trace to check the data of digital products in a certain clock cycle, reading out the internal status data of digital products recorded at a last time point before this clock cycle and the external port status data at said time point in the recorded simulation data; and
loading said digital products into a FPGA, setting the external port status data and the internal status data recorded at said time point as an initial status data of digital products, starting said FPGA to run and read out all internal status data of digital products clock by clock until running to a clock cycle that needs to be viewed;
wherein when the external port status data and the internal status data of digital products are recorded, a serial number of the clock cycle is taken as a timestamp to store the external port status data and the internal status data of digital products as ordered structured data.