| CPC G06F 16/215 (2019.01) [G06F 16/217 (2019.01); G06F 16/2282 (2019.01)] | 6 Claims |

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1. A compaction accelerator, comprising:
a direct memory access (DMA) controller configured to access one or more sorted string table (SST) files in a database system;
two or more merge tiles, which operate independent of the database system, that receive the one or more SST files from the DMA controller, each merge tile comprising merge tile components of:
two or more decoders, each of which converts one of the one or more SST files into a corresponding key-value (KV) format data stream, wherein the key-value (KV) format comprises an ordered set of key-value pairs;
a merge iterator that receives the KV format data stream from each of the two or more decoders, and combines the KV format data streams into a single KV format data stream;
at least one arbiter that generates one or more timing signals associated with each of the KV format data streams, the one or more timing signals configured to coordinate transfer of KV format data streams through the two or more merge tiles;
at least one multiplexer for selectively routing a data path through the two or more merge tiles;
at least one of the merge tile components is configured to be formatted by metadata information that accompanies the one or more SST files, the metadata information provided to the merge tile by an external resource that addresses the merge tile through an address associated with the merge tile;
at least one merge integrator that receives the single KV format data stream from each of the two or more merge tiles and produces a composite KV format data stream therefrom; and
the two or more merge tiles and the at least one merge integrator are implemented, at least partially, as hardware components.
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