US 12,380,034 B2
Extended attributes for shared page tables
Paul Blinzer, Carnation, WA (US); Anthony Asaro, Toronto (CA); Nippon HarshadKumar Raval, Mississauga (CA); Anthony Thomas Gutierrez, Seattle, WA (US); Leopold Grinberg, Belmont, MA (US); Millind Mittal, Saratoga, CA (US); and Samuel Richard Bayliss, Los Altos, CA (US)
Assigned to Advanced Micro Devices, Inc, Santa Clara, CA (US); and ATI Technologies ULC, Markham (CA)
Filed by Advanced Micro Devices, Inc, Santa Clara, CA (US); and ATI Technologies ULC, Markham (CA)
Filed on Jun. 30, 2023, as Appl. No. 18/217,291.
Prior Publication US 2025/0004949 A1, Jan. 2, 2025
Int. Cl. G06F 12/10 (2016.01); G06F 12/1009 (2016.01); G06F 12/14 (2006.01)
CPC G06F 12/1009 (2013.01) [G06F 12/1416 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A device, comprising:
an accelerator device; and
memory management circuitry to:
maintain a first page table and a second page table allocated to a process that invokes the accelerator device, the second page table including one or more extended attributes specific to the accelerator device, the one or more extended attributes differing from one or more additional extended attributes of a third page table allocated to an additional process that invokes an additional accelerator device;
receive a virtual memory address;
retrieve, from the first page table, a physical memory address corresponding to the virtual memory address; and
retrieve, from the second page table, the one or more extended attributes, wherein data is accessed from the physical memory address based on the one or more extended attributes.