US 12,380,033 B2
Refreshing cache regions using a memory controller and multiple tables
Douglas Raye Reed, Austin, TX (US); Al Loper, Austin, TX (US); and Terry Parks, Austin, TX (US)
Assigned to CENTAUR TECHNOLOGY, INC., Austin, TX (US)
Filed by CENTAUR TECHNOLOGY, INC., Austin, TX (US)
Filed on Jan. 21, 2022, as Appl. No. 17/581,110.
Prior Publication US 2023/0236985 A1, Jul. 27, 2023
Int. Cl. G06F 12/00 (2006.01); G06F 12/0891 (2016.01)
CPC G06F 12/0891 (2013.01) [G06F 2212/305 (2013.01)] 12 Claims
OG exemplary drawing
 
1. A controller in a microprocessor, the controller configured to manage accesses to dynamic random access memory (DRAM), the controller comprising:
a first table comprising first plural bitmasks, each of the first plural bitmasks corresponding to a respective memory page of cache lines, the respective memory page corresponding to a respective region in the DRAM, the controller configured to set a bit for one of the first plural bitmasks for each cache line of the memory page written to zero; and
a second table configured for storing second plural bitmasks, wherein the controller is configured to enter one of the second plural bitmasks as an entry into the second table and set a bit for the one of the second plural bitmasks when all bits of the one of the first plural bitmasks are set based on all of the cache lines of the memory page corresponding to the one of the first plural bitmasks being written to zero, wherein the first table is separate from the second table.