US 12,380,031 B2
Method and apparatus for designing cache memory structure based on artificial intelligence
Eui Young Chung, Seoul (KR); Min Jung Cho, Seoul (KR); Sang Hyup Lee, Seoul (KR); Do Hyeon Kim, Seoul (KR); and Seong Jae Eom, Seoul (KR)
Assigned to UIF (University Industry Foundation), Yonsei University, Seoul (KR)
Filed by UIF (University Industry Foundation), Yonsei University, Seoul (KR)
Filed on Dec. 28, 2023, as Appl. No. 18/399,517.
Claims priority of application No. 10-2022-0189714 (KR), filed on Dec. 29, 2022.
Prior Publication US 2024/0220413 A1, Jul. 4, 2024
Int. Cl. G06F 12/0877 (2016.01); G06F 12/0893 (2016.01)
CPC G06F 12/0877 (2013.01) [G06F 12/0893 (2013.01)] 13 Claims
OG exemplary drawing
 
1. A cache memory structure designing method for designing a structure of a cache memory of an accelerator, in a cache memory structure designing apparatus, the method comprising:
a memory access information extracting step of extracting a memory address of a cache memory accessed by a processing element array (PE array) at every time stamp for an application input to the accelerator;
a memory access pattern determining step of determining a memory access pattern for the application based on the memory addresses of the cache memory accessed over time; and
a cache structure design step of deriving a cache memory structure using a cache structure design model trained in advance based on a memory access pattern and generating cache structure design information for the cache memory structure.