US 12,380,028 B2
Data processing method and apparatus and heterogeneous system
Tao Li, Hangzhou (CN); Weibin Lin, Hangzhou (CN); Haocheng Liu, Hangzhou (CN); Lixia Xu, Hangzhou (CN); and Sheng Li, Shenzhen (CN)
Assigned to HUAWEI TECHNOLOGIES CO., LTD., Shenzhen (CN)
Filed by HUAWEI TECHNOLOGIES CO., LTD., Guangdong (CN)
Filed on Oct. 12, 2022, as Appl. No. 18/046,151.
Application 18/046,151 is a continuation of application No. PCT/CN2021/086703, filed on Apr. 12, 2021.
Claims priority of application No. 202010323587.5 (CN), filed on Apr. 22, 2020.
Prior Publication US 2023/0114242 A1, Apr. 13, 2023
Int. Cl. G06F 9/38 (2018.01); G06F 12/0815 (2016.01)
CPC G06F 12/0815 (2013.01) [G06F 9/3877 (2013.01); G06F 2212/1016 (2013.01); G06F 2212/621 (2013.01)] 11 Claims
OG exemplary drawing
 
1. A heterogeneous system, comprising:
a processor, a plurality of accelerators, and a plurality of secondary memories each connected to a corresponding one of the plurality of accelerators;
wherein the processor is configured to:
write to-be-processed data into a first secondary memory of the plurality of processors;
trigger a first accelerator of the plurality of accelerators to process the to-be-processed data in the first secondary memory according to a processing instruction, wherein the processing instruction carries an identifier of the processor and an accelerator identifier identifying one of the plurality of accelerators that is configured to execute the processing instruction;
wherein the first accelerator is configured to:
when the accelerator identifier is not an identifier of the first accelerator, write the to-be-processed data into a second secondary memory connected to a second accelerator indicated by the accelerator identifier; and
trigger the second accelerator to process the to-be-processed data according to the processing instruction; and
wherein the second accelerator is configured to:
process the to-be-processed data in the second secondary memory;
write a processing result of the to-be-processed data into the second secondary memory connected to the secondary accelerator; and
trigger, based on the identifier of the processor carried in the processing instruction, the processor to read the processing result from the second secondary memory connected to the secondary accelerator.