US 12,380,024 B2
Memory device, operating method of memory device, and storage device
Ji Seong Mun, Icheon-si (KR); Chan Keun Kwon, Icheon-si (KR); Ja Yoon Goo, Icheon-si (KR); Hyeon Cheon Seol, Icheon-si (KR); Sung Hwa Ok, Icheon-si (KR); and Young Seung Yoo, Icheon-si (KR)
Assigned to SK hynix Inc., Gyeonggi-do (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Jan. 19, 2024, as Appl. No. 18/417,840.
Claims priority of application No. 10-2023-0112889 (KR), filed on Aug. 28, 2023.
Prior Publication US 2025/0077425 A1, Mar. 6, 2025
Int. Cl. G06F 12/0802 (2016.01)
CPC G06F 12/0802 (2013.01) [G06F 2212/1044 (2013.01); G06F 2212/401 (2013.01)] 20 Claims
OG exemplary drawing
 
12. A method of operating a memory device, the method comprising:
generating compressed data obtained by compressing data read from a plurality of memory banks included in each of a plurality of memory planes;
merging compressed data corresponding to memory banks grouped as a merge group in response to at least one of a plurality of output control signals corresponding to at least one of the memory banks; and
outputting the merged data in response to at least one of the plurality of output control signals,
wherein the plurality of memory planes are grouped into memory plane groups, wherein each memory plane group comprises at least two memory planes sharing at least one peripheral circuit, and
wherein, in the merge group, at least some of the memory banks included in the same plane group are grouped.