US 12,380,023 B2
Providing adaptive cache bypass in processor-based devices
Suryanarayana Murthy Durbhakula, Hyderabad (IN)
Assigned to QUALCOMM Incorporated, San Diego, CA (US)
Filed by QUALCOMM Incorporated, San Diego, CA (US)
Filed on Sep. 2, 2022, as Appl. No. 17/929,525.
Prior Publication US 2024/0078178 A1, Mar. 7, 2024
Int. Cl. G06F 12/0802 (2016.01); G06F 12/0888 (2016.01)
CPC G06F 12/0802 (2013.01) [G06F 12/0888 (2013.01); G06F 2212/60 (2013.01)] 15 Claims
OG exemplary drawing
 
1. A processor-based device, comprising:
a processor comprising a cache;
the processor configured to:
calculate a cache result rate based on a first one or more outcomes of a corresponding first one or more cache requests to a cache region of the cache during a sampling period, wherein the cache region comprises the entire cache;
determine that the cache result rate fails to satisfy a cache result requirement;
responsive to determining that the cache result rate fails to satisfy the cache result requirement, restrict access to the cache region of the cache subsequent to the sampling period by being configured to disable the cache;
subsequent to a predetermined reset interval, re-enable the cache; and
invalidate contents of the cache.