US 12,380,019 B2
System memory address decoding for interleaving addresses across physical regions of a system-on-chip (SOC) and across shared memory resources in a processor-based system
Keith Robert Pflederer, Mountain View, CA (US)
Assigned to QUALCOMM Incorporated, San Diego, CA (US)
Filed by QUALCOMM Incorporated, San Diego, CA (US)
Filed on Nov. 16, 2023, as Appl. No. 18/511,079.
Claims priority of provisional application 63/491,506, filed on Mar. 21, 2023.
Prior Publication US 2024/0320140 A1, Sep. 26, 2024
Int. Cl. G06F 12/02 (2006.01)
CPC G06F 12/023 (2013.01) 21 Claims
OG exemplary drawing
 
1. A processor-based system for determining a target identification for a memory request comprising:
a processor configured to determine at least one configuration parameter comprising a plurality of available shared memory resources on a system-on-chip (SoC) in one or more physical regions, each of the plurality of available shared memory resources associated with a target identifier, the at least one configuration parameter further comprising:
a plurality of hashing regions for system memory addresses which are interleaved across the one or more physical regions and one or more of the plurality of available shared memory resources within a physical region of the one or more physical regions, each hashing region corresponding to a hash circuit and a unique combination of the one or more physical regions and one or more available memory resources; and
in response to receiving the memory request having a system memory address:
the processor is configured to determine a first hashing region of the plurality of hashing regions in which the system memory address resides;
the processor is configured to hash the system memory address based on a first hash circuit corresponding to the first hashing region to identify a first physical region;
the processor is configured to hash the system memory address based on a second hash circuit corresponding to the first hashing region to select a first available shared memory resource within the first physical region;
the processor is configured to determine a first target identifier of the first available shared memory resource; and
the processor is configured to route and perform the memory request to the first available shared memory resource based on the first target identifier.