US 12,379,991 B2
Error detection event mechanism
Giuseppe Cariello, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Dec. 29, 2021, as Appl. No. 17/564,843.
Claims priority of provisional application 63/140,666, filed on Jan. 22, 2021.
Prior Publication US 2022/0237079 A1, Jul. 28, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 11/00 (2006.01); G06F 11/07 (2006.01); G06F 11/10 (2006.01); G06F 11/362 (2025.01)
CPC G06F 11/1068 (2013.01) [G06F 11/0757 (2013.01); G06F 11/0772 (2013.01); G06F 11/0793 (2013.01); G06F 11/3656 (2013.01)] 9 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a memory device;
a register; and
a control circuit coupled with the memory device and configured to cause the apparatus to:
identify a fault condition of the apparatus;
transmit, to a host system, a message indicating a first indication that the fault condition exists at the apparatus based at least in part on identifying the fault condition;
set, in the register, a second indication indicating a type of the fault condition based at least in part on identifying the fault condition;
initiate the apparatus to enter a safe mode of operation based at least in part on transmitting the message;
refrain from performing an operation based at least in part on initiating the apparatus to enter the safe mode of operation;
receive, from the host system, a command to exit the safe mode of operation;
exit the safe mode of operation based at least in part on receiving the command; and
perform a recovery procedure based at least in part on the first indication and the second indication, wherein performing the recovery procedure is based at least in part on exiting the safe mode of operation.