US 12,379,969 B2
Workgroup hierarchical core structures for building real-time workgroup systems
Ivan Chung-Shung Hwang, North Tustin, CA (US)
Assigned to HT RESEARCH, INC., North Tustin, CA (US)
Filed by HT Research Inc., North Tustin, CA (US)
Filed on Jan. 5, 2024, as Appl. No. 18/405,797.
Application 18/405,797 is a continuation of application No. 18/116,541, filed on Mar. 2, 2023, granted, now 11,868,813.
Application 18/116,541 is a continuation of application No. 17/484,230, filed on Sep. 24, 2021, granted, now 11,609,795, issued on Mar. 21, 2023.
Application 17/484,230 is a continuation of application No. 16/270,097, filed on Feb. 7, 2019, granted, now 11,132,236, issued on Sep. 28, 2021.
Claims priority of provisional application 62/627,664, filed on Feb. 7, 2018.
Prior Publication US 2024/0211318 A1, Jun. 27, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 11/07 (2006.01); G06F 9/50 (2006.01); G06F 11/16 (2006.01); G06F 11/20 (2006.01); G06F 13/16 (2006.01); H04L 41/0663 (2022.01); H04L 41/0668 (2022.01)
CPC G06F 9/5072 (2013.01) [G06F 11/1666 (2013.01); G06F 11/2007 (2013.01); G06F 11/2041 (2013.01); G06F 13/1663 (2013.01); H04L 41/0663 (2013.01); H04L 41/0668 (2013.01)] 37 Claims
OG exemplary drawing
 
1. A computer system comprising:
an execution pylon coupled to a fail-over pylon through a plurality of workgroup fail-over links, the execution pylon comprising:
a top control block;
a mid-memory block coupled to the top control block; and
a base attribute block coupled to the mid-memory block;
wherein the base attribute block comprises:
a first-type base block;
a plurality of second-type base blocks comprising a first second-type base block and a second second-type base block, each of the first and second second-type base blocks coupled to the first-type base block;
a plurality of third-type base blocks comprising a first third-type base block and a second third-type base block, each of the first and second third-type base blocks coupled to the plurality of second-type base block so that the first second-type base block is disposed between the first-type base block and the first third-type base block and the second second-type base block is disposed between the first-type base block and the second third-type base block,
wherein the first third-type base block is coupled to the mid-memory block.