US 12,379,932 B2
Execution of instructions requiring access to an array register
Xiaoyang Shen, Valbonne (FR); Shun Wan, Cambridge (GB); Zichao Xie, Cambourne (GB); and Scott Ryan Tancock, Haverhill (GB)
Assigned to Arm Limited, Cambridge (GB)
Filed by Arm Limited, Cambridge (GB)
Filed on Dec. 22, 2023, as Appl. No. 18/393,833.
Prior Publication US 2025/0208876 A1, Jun. 26, 2025
Int. Cl. G06F 9/38 (2018.01); G06F 9/30 (2018.01)
CPC G06F 9/3836 (2013.01) [G06F 9/30098 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a plurality of registers configured to store data, the plurality of registers comprising at least one array register comprising a plurality of array regions;
processing circuitry configured to receive issued instructions and to perform processing operations identified in the issued instructions; and
control circuitry comprising buffer circuitry to store one or more instructions prior to execution by the processing circuitry, the control circuitry responsive to receipt of an instruction requiring access to two or more array regions of the plurality of array regions:
to decompose the instruction into two or more execution parts, each of the two or more execution parts corresponding to one of the two or more array regions; and
for each execution part of the two or more execution parts, to delay issuing the execution part as one of the issued instructions until it is predicted that the execution part can be processed hazard free by the processing circuitry, wherein the control circuitry is capable of issuing the two or more execution parts of the instruction in different cycles selected based on when it is predicted that each of the two or more execution parts can be processed hazard free.