| CPC G06F 9/30036 (2013.01) [G06F 9/30134 (2013.01)] | 17 Claims |
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1. Apparatus comprising:
processing circuitry to perform data processing operations in response to a sequence of instructions; and
register bank circuitry to provide registers for holding data values that are subject to the data processing operations and comprising at least one read port via which data values are read from the registers,
wherein the register bank circuitry further comprises register access circuitry responsive to receipt from the processing circuitry of a register selection vector to perform a read address compression procedure on a vector of read addresses, wherein the register selection vector comprises element validity indicators corresponding to address elements of the vector of read addresses,
wherein the read address compression procedure comprises:
identifying selected element positions and non-selected element positions based on the element validity indicators; and
shifting in the vector of read addresses a set of active read addresses given by the selected element positions in a predetermined direction towards a predetermined element position, such that the set of active read addresses forms a contiguous group in the vector of read addresses ending on one side at the predetermined element position,
and wherein the register access circuitry is configured to cause a read vector of data values identified by the set of active read addresses to be read out from the registers via a selected read port of the at least one read port.
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