US 12,379,899 B2
Performing multiple bit computation and convolution in memory
Shahzad Nazar, Fremont, CA (US); Bharan Giridhar, Palo Alto, CA (US); Mohamed H. Abu-Rahma, Mountain View, CA (US); Ajay Bhatia, Saratoga, CA (US); Mayur V. Joshi, San Carlos, CA (US); Yildiz Sinangil, Campbell, CA (US); and Aravind Kandala, San Jose, CA (US)
Assigned to Apple Inc., Cupertino, CA (US)
Filed by Apple Inc., Cupertino, CA (US)
Filed on Jan. 19, 2024, as Appl. No. 18/417,868.
Application 18/417,868 is a division of application No. 16/953,093, filed on Nov. 19, 2020, granted, now 11,914,973.
Prior Publication US 2024/0231758 A1, Jul. 11, 2024
Int. Cl. G06F 7/544 (2006.01); G06F 7/523 (2006.01); G06F 17/15 (2006.01); G06N 20/00 (2019.01); H03M 1/46 (2006.01)
CPC G06F 7/5443 (2013.01) [G06F 7/523 (2013.01); G06F 17/15 (2013.01); H03M 1/46 (2013.01); G06N 20/00 (2019.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a first memory array circuit including a plurality of columns, wherein a given column of the plurality of columns is configured to store a respective weight value of a plurality of weight values, and wherein the respective weight value includes a plurality of weight bits;
a control circuit configured to perform a multiplication operation across a plurality of cycles, wherein to perform a given cycle of the plurality of cycles, the control circuit is configured to retrieve a weight bit from respective columns of the plurality of columns to form a set of weight bits, the weight bit being of a respective one of the plurality of weight values;
a decoder circuit configured to, during the given cycle, combine, for each weight bit of the set of weight bits, that weight bit with an operand bit, from one of a plurality of operands that corresponds to a weight value that includes that weight bit, to generate a portion of a given product bit set of a plurality of product bit sets; and
an adder circuit configured, in response to a determination that the multiplication operation has completed, to combine the plurality of product bit sets to generate a result.