US 12,379,855 B2
Semiconductor memory device including a cyclic redundancy check engine and memory system including the same
Sungrae Kim, Seoul (KR); Hyeran Kim, Uiwang-si (KR); Myungkyu Lee, Seoul (KR); Chisung Oh, Suwon-si (KR); Kijun Lee, Seoul (KR); Sunghye Cho, Hwaseong-si (KR); and Sanguhn Cha, Suwon-si (KR)
Assigned to Samsung Electronics Co., Ltd., (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Feb. 27, 2024, as Appl. No. 18/588,599.
Application 18/588,599 is a continuation of application No. 17/743,137, filed on May 12, 2022, granted, now 11,947,810.
Claims priority of application No. 10-2021-0069726 (KR), filed on May 31, 2021.
Prior Publication US 2024/0201868 A1, Jun. 20, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0619 (2013.01) [G06F 3/0655 (2013.01); G06F 3/0656 (2013.01); G06F 3/0679 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of operating a semiconductor memory device that includes a memory cell array comprising a plurality of volatile memory cells coupled to respective ones of a plurality of word-lines and respective ones of a plurality of bit-lines and a cyclic redundancy check (CRC) engine, the method comprising:
detecting, by the CRC engine, an error in a main data and a system parity data received from a memory controller through a link, the memory controller being external to the semiconductor memory device;
generating, by the CRC engine, an error flag indicating whether the error that was detected corresponds to either a first type of error associated with the link or a second type of error associated with the volatile memory cells based on the system parity data; and
transmitting, by the CRC engine, the error flag to the memory controller.