US 12,379,843 B2
Chipset attached random access memory
William Robert Alverson, Del Valle, TX (US); Amitabh Mehra, Fort Collins, CO (US); Jerry Anton Ahrens, Sister Bay, WI (US); Grant Evan Ley, Eden, UT (US); Anil Harwani, Austin, TX (US); and Joshua Taylor Knight, Georgetown, TX (US)
Assigned to Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed by Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed on Aug. 12, 2022, as Appl. No. 17/887,245.
Prior Publication US 2024/0053891 A1, Feb. 15, 2024
Int. Cl. G06F 3/06 (2006.01); G06F 15/78 (2006.01)
CPC G06F 3/061 (2013.01) [G06F 3/0655 (2013.01); G06F 3/0673 (2013.01); G06F 15/7803 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system comprising:
a processing unit package including a processing unit and a memory controller;
a system memory coupled to the processing unit package, the system memory including a dynamic random access memory, the memory controller being configured to read data from and write data to the system memory;
an input/output expander including a random access memory controller;
a chipset link coupling the processing unit package to the input/output expander; and
a chipset attached dynamic random access memory directly coupled to the input/output expander and separate from the system memory, the chipset attached dynamic random access memory controlled by the random access memory controller.