| CPC G06F 1/3296 (2013.01) | 20 Claims |
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15. A method of controlling temperature in an electronic device including an intellectual property (IP) block, the method comprising:
generating an operating clock using a Phase-Locked Loop (PLL);
providing the operating clock to the IP block, wherein a temperature of the IP block is related to a frequency of the operating clock;
providing a supply voltage to a critical path monitor (CPM) of a dynamic voltage frequency scaling (DVFS) block, the DVFS block being configured to perform dynamic voltage frequency scaling on the IP block, and the CPM being configured to generate a speed code that indicates an operating speed of the operating clock;
determining a target frequency for the operating clock;
determining, based upon the speed code, a current frequency for the operating clock;
comparing the target frequency and the current frequency to generate frequency comparison results;
generating deciding results in response to the frequency comparison results; and
controlling a level of the supply voltage in response to the deciding results.
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