US 12,379,740 B2
Technique to mitigate clock generation failure at high input clock slew
Jaspal Singh Shah, Hsinchu (TW); and Atul Katoch, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jun. 29, 2023, as Appl. No. 18/344,087.
Claims priority of provisional application 63/482,309, filed on Jan. 31, 2023.
Prior Publication US 2024/0255982 A1, Aug. 1, 2024
Int. Cl. G06F 1/10 (2006.01); G06F 1/12 (2006.01)
CPC G06F 1/10 (2013.01) [G06F 1/12 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A clock generation circuit, comprising:
a first transistor having a gate connected to a clock signal;
a second transistor, connected in parallel to the first transistor;
a third transistor connected to a first reference voltage and the first transistor;
a fourth transistor connected to the first transistor and a second reference voltage; and
a driving circuit, coupled to the second transistor, and comprising an input and an output,
wherein the input of the driving circuit is connected to the clock signal, the output of the driving circuit is connected to a gate of the second transistor, and the driving circuit is configured to reduce a slew of the clock signal, the clock signal is an external clock signal, and the clock generation circuit is configured to generate an internal clock signal from the external clock signal.