| CPC G01R 31/2886 (2013.01) [G01R 1/0408 (2013.01); G01R 31/2879 (2013.01)] | 25 Claims |

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1. A semiconductor test system, comprising:
a single test fixture including a plurality of test cells disposed on the single test fixture and arranged in parallel rows and columns, wherein each test cell on the single test fixture has the same arrangement including a housing accommodating one and only one device under test (DUT) disposed in a DUT placement area within the housing, and an electrical test circuit disposed within the housing solely dedicated for the one and only one DUT and containing test circuitry dedicated to perform simultaneous, real-time voltage and current testing solely for the one and only one DUT within its test cell; and
a user interface displaying the real-time voltage and current testing for all test cells simultaneously.
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