US 12,379,411 B2
Circuit and method for testing a circuit
Alessio Ciarcia, Munich (DE)
Assigned to Infineon Technologies AG, Neubiberg (DE)
Filed by Infineon Technologies AG, Neubiberg (DE)
Filed on Sep. 25, 2023, as Appl. No. 18/473,354.
Application 18/473,354 is a continuation of application No. 17/953,347, filed on Sep. 27, 2022.
Prior Publication US 2024/0103067 A1, Mar. 28, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G01R 31/28 (2006.01)
CPC G01R 31/2851 (2013.01) 10 Claims
OG exemplary drawing
 
1. A circuit, comprising:
a plurality of scan flip-flops including a sequence of scan flip-flops, wherein at least some scan flip-flops of the sequence of scan flip-flops are wrapper scan flip-flops, each scan flip-flop of the sequence of scan flip-flops having a D input, a test enable input, a test input and a data output,
wherein the circuit comprises, for each scan flip-flop of at least a subset of the scan flip-flops of the sequence of scan flip-flops, at the scan flip-flop's test input a respective test input circuit comprising a plurality of logic gates, wherein the plurality of logic gates of the test input circuit is configured to,
when supplied with a mode control signal having a first value indicating a shift mode, connect the test input to the output of the scan flip-flop preceding the scan flip-flop in the sequence such that the test input of the scan flip-flop is supplied with the content of the scan flip-flop preceding the scan flip-flop in the sequence and
when supplied with the mode control signal having a second value indicating a capture mode, connect the test input to an output of a subcircuit of the circuit, wherein the subcircuit is under test, such that the test input of the flip-flop is supplied with a value depending on a test result provided by the subcircuit.