CPC G06F 3/0625 (2013.01) [G06F 3/0659 (2013.01); G06F 3/0679 (2013.01); G11C 14/0063 (2013.01); G11C 16/0408 (2013.01)] | 20 Claims |
1. A memory system comprising:
a communication interface; and
a controller circuit coupled to the communication interface, wherein the controller circuit comprises:
a load reduction memory buffer coupled between a host interface and a volatile memory interface;
a register block to store one or more parameters or settings, wherein the one or more parameters or settings comprises at least one of a speed parameter, a frequency parameter, or a latency parameter of a volatile memory coupled to the volatile memory interface; and
data buffers to provide speed matching between the volatile memory interface and a non-volatile memory interface, wherein the controller circuit is to:
execute a first set of one or more commands according to the one or more parameters or settings;
receive a request to update at least one of the one or more parameters or settings or the first set of one or more commands;
update the at least one of the one or more parameters or settings to one or more updated parameters or settings or the first set of one or more commands to an updated set of one or more commands; and
send, to a non-volatile memory coupled to the non-volatile memory interface, a copy of the at least one of the one or more updated parameters or settings or the updated set of one or more commands such that the at least one of the one or more updated parameters or settings or the updated set of one or more commands are preserved after a power cycle.
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