| CPC H10N 70/253 (2023.02) [G11C 13/0004 (2013.01); H10B 63/30 (2023.02); H10N 70/021 (2023.02); H10N 70/231 (2023.02)] | 20 Claims |
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1. An integrated circuit, comprising:
a first chip including a memory cell, the memory cell including:
a transistor including:
a plurality of semiconductor nanosheets;
a gate dielectric surrounding the semiconductor nanosheets;
a gate electrode including a gate metal surrounding the semiconductor nanosheets and separated from the semiconductor nanosheets by the gate dielectric;
a first semiconductor source/drain terminal coupled to the semiconductor nanosheets; and
a second semiconductor source/drain terminal coupled to the semiconductor nanosheets;
a phase change memory element electrically coupled to the transistor; and
a first electrode coupled between the phase change memory element and the transistor and having a top surface coupled to a bottom surface of the first semiconductor source/drain terminal; and
a second chip bonded to the first chip, wherein the transistor is positioned between the phase change memory element and the second chip.
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