US 12,376,427 B2
Display device using semiconductor light emitting diode
Changseo Park, Seoul (KR); Kiseong Jeon, Seoul (KR); Jinhong Park, Seoul (KR); and Hwankuk Yuh, Seoul (KR)
Assigned to LG ELECTRONICS INC., Seoul (KR)
Filed by LG ELECTRONICS INC., Seoul (KR)
Filed on Feb. 7, 2023, as Appl. No. 18/106,671.
Application 18/106,671 is a continuation of application No. 15/751,970, granted, now 11,605,757, previously published as PCT/KR2016/009256, filed on Aug. 22, 2016.
Claims priority of application No. 10-2015-0118163 (KR), filed on Aug. 21, 2015; and application No. 10-2016-0099575 (KR), filed on Aug. 4, 2016.
Prior Publication US 2023/0197892 A1, Jun. 22, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H10H 20/813 (2025.01); H01L 25/075 (2006.01); H05B 33/10 (2006.01); H05B 33/14 (2006.01); H05B 33/22 (2006.01); H05K 1/11 (2006.01); H10H 20/831 (2025.01); H10H 20/84 (2025.01); H10H 20/857 (2025.01); H10H 20/851 (2025.01)
CPC H10H 20/813 (2025.01) [H01L 25/0753 (2013.01); H05B 33/10 (2013.01); H05B 33/14 (2013.01); H05B 33/22 (2013.01); H05K 1/111 (2013.01); H10H 20/8312 (2025.01); H05K 2201/0145 (2013.01); H10H 20/84 (2025.01); H10H 20/8512 (2025.01); H10H 20/857 (2025.01); Y02B 20/40 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A display device, comprising:
a substrate having a plurality of metal pads; and
a plurality of semiconductor light emitting devices electrically connected to the metal pads; and
a plurality of black matrixes disposed between each of the plurality of semiconductor light emitting devices,
wherein the substrate comprises a planarizing layer having a plurality of self-assembly regions spaced from each other,
wherein the planarizing layer comprises an insulating material filled between the plurality of semiconductor light emitting devices,
wherein the planarizing layer having the insulating material is disposed on a bottom surface of a respective semiconductor light emitting device among the plurality of semiconductor light emitting devices,
wherein the respective semiconductor light emitting device is disposed in a respective self-assembly region, and the respective semiconductor light emitting device comprises an n-type semiconductor layer, an active layer and a p-type semiconductor layer, a conductive electrode on the p-type semiconductor layer; and a passivation layer configured to surround the respective semiconductor light emitting device and including a through hole through which the conductive electrode is exposed,
wherein the conductive electrode comprises a protruding portion protruding through the through hole of the passivation layer and overlapping outer surfaces of the passivation layer,
wherein the protruding portion of the conductive electrode contacts a corresponding metal pad,
wherein a width of the protruding portion of the conductive electrode is greater than a width of the corresponding metal pad,
wherein each of the plurality of semiconductor light emitting devices comprises an n-type electrode on the n-type semiconductor layer,
wherein each of the n-type electrodes is vertically overlapped with each of the conductive electrodes,
wherein each of the plurality of semiconductor light emitting devices comprises an n-type electrode on the n-type semiconductor layer,
wherein each of the n-type electrodes is disposed between adjacent two black matrixes among the plurality of black matrixes,
wherein each of the n-type electrodes is vertically overlapped with each of the conductive electrodes, and
wherein a lateral width of the conductive electrode is less than a lateral width of the each of the n-type electrodes.