| CPC H10F 39/809 (2025.01) [H01L 24/08 (2013.01); H10F 39/811 (2025.01); H01L 2224/08145 (2013.01)] | 20 Claims |

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1. A semiconductor apparatus comprising:
a first semiconductor component comprising a cell array, a first plurality of pads and a plurality of wirings; and
a second semiconductor component comprising a second plurality of pads connected to the first semiconductor component,
wherein the first semiconductor component and the second semiconductor component overlap with each other, the first plurality of pads of the first semiconductor component and the second plurality of pads of the second semiconductor component are directly bonded at a joint surface and a first insulating member of the first semiconductor component and a second insulating member of the second semiconductor component are directly bonded at the joint surface,
wherein the cell array comprises a plurality of cells arranged in a first direction and a second direction that crosses the first direction,
wherein the first plurality of pads and the second plurality of pads areis arranged on a plane along the first direction and the second direction to overlap with the cell array,
wherein the plurality of cells comprises a first cell, a second cell, and a third cell,
wherein the first cell, the second cell, and the third cell are arranged along the first direction in order,
wherein the plurality of wirings comprises:
a first wiring connected to the first cell;
a second wiring connected to the first cell and the third cell; and
a third wiring connected to the third cell,
wherein the second plurality of pads comprises:
a first pad connected to the first wiring;
a second pad connected to the second wiring; and
a third pad connected to the third wiring, and
wherein the first pad, the second pad, and the third pad are arranged along the first direction in order.
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