US 12,376,382 B2
3D semiconductor devices and structures with metal layers
Zvi Or-Bach, Haifa (IL); and Brian Cronquist, Klamath Falls, OR (US)
Assigned to Monolithic 3D Inc., Klamath Falls, OR (US)
Filed by Monolithic 3D Inc., Klamath Falls, OR (US)
Filed on Nov. 25, 2024, as Appl. No. 18/959,033.
Application 18/959,033 is a continuation in part of application No. 18/668,218, filed on May 19, 2024, granted, now 12,199,093.
Application 18/668,218 is a continuation in part of application No. 18/603,526, filed on Mar. 13, 2024, granted, now 12,027,518, issued on Jul. 2, 2024.
Application 18/603,526 is a continuation in part of application No. 18/128,505, filed on Mar. 30, 2023, granted, now 11,984,445, issued on May 14, 2024.
Application 18/128,505 is a continuation in part of application No. 17/827,705, filed on May 28, 2022, granted, now 11,646,309, issued on May 9, 2023.
Application 17/827,705 is a continuation in part of application No. 16/936,352, filed on Jul. 22, 2020, granted, now 11,374,118, issued on Jun. 28, 2022.
Application 16/936,352 is a continuation in part of application No. 16/242,300, filed on Jan. 8, 2019, granted, now 10,910,364, issued on Feb. 2, 2021.
Application 16/242,300 is a continuation in part of application No. 15/922,913, filed on Mar. 16, 2018, granted, now 10,354,995.
Application 15/922,913 is a continuation in part of application No. 15/409,740, filed on Jan. 19, 2017, granted, now 9,941,332, issued on Apr. 10, 2018.
Application 15/409,740 is a continuation in part of application No. 15/224,929, filed on Aug. 1, 2016, granted, now 9,853,089, issued on Dec. 26, 2017.
Application 15/224,929 is a continuation in part of application No. 14/514,386, filed on Oct. 15, 2014, granted, now 9,406,670, issued on Aug. 2, 2016.
Application 14/514,386 is a continuation of application No. 13/492,382, filed on Jun. 8, 2012, granted, now 8,907,442, issued on Dec. 9, 2014.
Application 13/492,382 is a continuation of application No. 13/246,384, filed on Sep. 27, 2011, granted, now 8,237,228, issued on Aug. 7, 2012.
Application 13/246,384 is a continuation of application No. 12/900,379, filed on Oct. 7, 2010, granted, now 8,395,191, issued on Mar. 12, 2013.
Application 12/900,379 is a continuation in part of application No. 12/859,665, filed on Aug. 19, 2010, granted, now 8,405,420, issued on Mar. 26, 2013.
Application 12/859,665 is a continuation in part of application No. 12/849,272, filed on Aug. 3, 2010, granted, now 7,986,042, issued on Jul. 26, 2011.
Application 12/859,665 is a continuation in part of application No. 12/847,911, filed on Jul. 30, 2010, granted, now 7,960,242, issued on Jun. 14, 2011.
Application 12/849,272 is a continuation in part of application No. 12/797,493, filed on Jun. 9, 2010, granted, now 8,115,511.
Application 12/849,272 is a continuation in part of application No. 12/792,673, filed on Jun. 2, 2010, granted, now 7,964,916, issued on Jun. 21, 2011.
Application 12/849,272 is a continuation in part of application No. 12/706,520, filed on Feb. 16, 2010, abandoned.
Application 12/797,493 is a continuation in part of application No. 12/577,532, filed on Oct. 12, 2009, abandoned.
Application 12/792,673 is a continuation in part of application No. 12/577,532, filed on Oct. 12, 2009, abandoned.
Prior Publication US 2025/0098325 A1, Mar. 20, 2025
This patent is subject to a terminal disclaimer.
Int. Cl. H10D 88/00 (2025.01); G03F 9/00 (2006.01); H01L 21/762 (2006.01); H01L 21/768 (2006.01); H01L 23/367 (2006.01); H01L 23/48 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 23/532 (2006.01); H01L 23/544 (2006.01); H10B 10/00 (2023.01); H10B 12/00 (2023.01); H10B 20/00 (2023.01); H10B 41/20 (2023.01); H10B 43/20 (2023.01); H10D 10/01 (2025.01); H10D 10/40 (2025.01); H10D 30/01 (2025.01); H10D 30/67 (2025.01); H10D 30/83 (2025.01); H10D 30/87 (2025.01); H10D 62/83 (2025.01); H10D 64/01 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/85 (2025.01); H10D 84/90 (2025.01); H10D 86/00 (2025.01); H10D 86/01 (2025.01); H10D 89/10 (2025.01); H01L 21/268 (2006.01); H01L 23/00 (2006.01); H10D 84/83 (2025.01)
CPC H10D 88/00 (2025.01) [G03F 9/7076 (2013.01); G03F 9/7084 (2013.01); H01L 21/76254 (2013.01); H01L 21/76898 (2013.01); H01L 23/367 (2013.01); H01L 23/481 (2013.01); H01L 23/5226 (2013.01); H01L 23/528 (2013.01); H01L 23/53214 (2013.01); H01L 23/53228 (2013.01); H01L 23/544 (2013.01); H10B 10/00 (2023.02); H10B 10/125 (2023.02); H10B 12/053 (2023.02); H10B 12/09 (2023.02); H10B 12/50 (2023.02); H10B 20/00 (2023.02); H10B 41/20 (2023.02); H10B 43/20 (2023.02); H10D 10/051 (2025.01); H10D 10/40 (2025.01); H10D 30/0512 (2025.01); H10D 30/061 (2025.01); H10D 30/6727 (2025.01); H10D 30/6728 (2025.01); H10D 30/6733 (2025.01); H10D 30/6735 (2025.01); H10D 30/6737 (2025.01); H10D 30/6743 (2025.01); H10D 30/83 (2025.01); H10D 30/87 (2025.01); H10D 62/83 (2025.01); H10D 64/027 (2025.01); H10D 84/0186 (2025.01); H10D 84/038 (2025.01); H10D 84/85 (2025.01); H10D 84/907 (2025.01); H10D 84/998 (2025.01); H10D 86/01 (2025.01); H10D 86/201 (2025.01); H10D 88/01 (2025.01); H10D 89/10 (2025.01); H01L 21/268 (2013.01); H01L 24/73 (2013.01); H01L 2223/5442 (2013.01); H01L 2223/54426 (2013.01); H01L 2223/54453 (2013.01); H01L 2224/16145 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/45124 (2013.01); H01L 2224/45147 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48227 (2013.01); H01L 2224/73204 (2013.01); H01L 2224/73253 (2013.01); H01L 2224/73265 (2013.01); H01L 2924/00011 (2013.01); H01L 2924/10253 (2013.01); H01L 2924/12032 (2013.01); H01L 2924/1301 (2013.01); H01L 2924/1305 (2013.01); H01L 2924/13062 (2013.01); H01L 2924/13091 (2013.01); H01L 2924/14 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/181 (2013.01); H01L 2924/3011 (2013.01); H01L 2924/3025 (2013.01); H10D 64/017 (2025.01); H10D 84/83 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, the semiconductor device comprising:
a first level comprising a first single crystal silicon layer and a plurality of first transistors;
a first metal layer;
a second metal layer,
wherein interconnection of said plurality of first transistors comprises said first metal layer and said second metal layer;
a second level comprising a plurality of second transistors, said second level disposed over said first level;
a third level comprising a plurality of third transistors, said third level disposed over said second level;
a third metal layer disposed over said third level;
a fourth metal layer disposed over said third metal layer;
a fourth level comprising a second single crystal silicon layer,
wherein said fourth level is disposed over said fourth metal layer,
wherein each of said plurality of second transistors comprises a metal gate,
wherein said second metal layer comprises a power delivery network; and
a via disposed through said second level and through said third level,
wherein each of said plurality of third transistors comprises a metal gate,
wherein said second level comprises a first array of memory cells,
wherein said third level comprises a second array of memory cells, and
wherein said first level comprises input and output (“IO”) circuits as part of connections of said device to external devices.