US 12,376,332 B2
Edge termination structures for semiconductor devices
Edward Robert Van Brunt, Raleigh, NC (US); and Thomas E. Harrington, III, Carrollton, TX (US)
Assigned to Wolfspeed, Inc., Durham, NC (US)
Filed by Wolfspeed, Inc., Durham, NC (US)
Filed on Feb. 2, 2023, as Appl. No. 18/163,824.
Application 18/163,824 is a continuation of application No. 17/031,365, filed on Sep. 24, 2020, granted, now 11,600,724.
Prior Publication US 2023/0178650 A1, Jun. 8, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H10D 30/65 (2025.01); H10D 62/10 (2025.01); H10D 62/832 (2025.01)
CPC H10D 30/655 (2025.01) [H10D 62/105 (2025.01); H10D 62/8325 (2025.01)] 30 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a drift region comprising a first doping type;
an active region comprising a portion of the drift region;
an edge termination region in the drift region and arranged along a perimeter of the active region, the edge termination region comprising a plurality of sub-regions of a second doping type that is opposite the first doping type;
a first electrode electrically connected to the edge termination region, the first electrode configured to be coupled to a first potential when the semiconductor device is electrically activated;
a first passivation layer on the edge termination region; and
a second passivation layer on the edge termination region,
wherein the first passivation layer extends continuously over at least two adjacent sub-regions of the second doping type, and
wherein the second passivation layer extends into the active region and is positioned in between a gate interconnect and a source interconnect.