US 12,376,302 B2
Semiconductor memory device and method for manufacturing semiconductor memory device
Saho Ohsawa, Yokkaichi (JP); Kenichi Fujii, Yokkaichi (JP); Takashi Fukushima, Yokkaichi (JP); Hiroyuki Ohtori, Yokkaichi (JP); Kaihei Katou, Yokkaichi (JP); Masaki Kato, Yokkaichi (JP); Ryosuke Sawabe, Yokkaichi (JP); and Yuji Sakai, Yokkaichi (JP)
Assigned to Kioxia Corporation, Tokyo (JP)
Filed by Kioxia Corporation, Tokyo (JP)
Filed on Jun. 9, 2022, as Appl. No. 17/806,111.
Claims priority of application No. 2022-043357 (JP), filed on Mar. 18, 2022.
Prior Publication US 2023/0301088 A1, Sep. 21, 2023
Int. Cl. H10D 64/68 (2025.01); H10B 43/27 (2023.01); H10D 30/69 (2025.01)
CPC H10B 43/27 (2023.02) [H10D 30/694 (2025.01); H10D 64/685 (2025.01)] 14 Claims
OG exemplary drawing
 
1. A semiconductor memory device, comprising:
a semiconductor layer extending in a first direction;
a first gate electrode layer containing at least one element selected from a group consisting of molybdenum (Mo), tungsten (W), ruthenium (Ru), and cobalt (Co);
a first insulating layer provided between the semiconductor layer and the first gate electrode layer;
a charge storage layer provided between the first insulating layer and the first gate electrode layer, the charge storage layer extending in the first direction;
a second insulating layer provided between the charge storage layer and the first gate electrode layer, the second insulating layer extending in the first direction;
a third insulating layer including a first portion, a second portion, and a third portion, the first portion being provided between the second insulating layer and the first gate electrode layer; and
a metal oxide layer provided between the third insulating layer and the gate electrode layer and containing a first metal element selected from a group consisting of titanium (Ti), molybdenum (Mo), tungsten (W), and tantalum (Ta),
wherein the second portion and the third portion face in the first direction, and the first gate electrode layer is provided between the second portion and the third portion in the first direction.
 
11. A semiconductor memory device, comprising:
a semiconductor layer extending in a first direction;
a first gate electrode layer containing molybdenum (Mo);
a first insulating layer provided between the semiconductor layer and the gate electrode layer;
a charge storage layer provided between the first insulating layer and the first gate electrode layer, the charge storage layer extending in the first direction;
a second insulating layer provided between the charge storage layer and the first gate electrode layer and containing silicon (Si) and oxygen (O), the second insulating layer extending in the first direction; and
a third insulating layer including a first portion, a second portion, and a third portion, the first portion being provided between the second insulating layer and the first gate electrode layer and containing aluminum (Al), oxygen (O), and nitrogen (N),
wherein the second portion and the third portion face in the first direction, and the first gate electrode layer is provided between the second portion and the third portion in the first direction.