| CPC H04W 68/005 (2013.01) [H04W 48/10 (2013.01)] | 17 Claims |

|
1. An electronic device comprising:
memory;
a communication circuitry; and
a communication processor,
wherein the communication processor is configured to:
identify a first time of receiving a paging message and a second time of receiving a synchronization signal/physical broadcast channel (SS/PBCH) block;
identify whether an interval between the first time and the second time is greater than or equal to a specified value being related to a reception periodicity of the SS/PBCH block,
based on the identification that the interval between the first time and the second time is less than the specified value,
receive a first SS/PBCH block,
receive the paging message after receiving the first SS/PBCH block, and
process the paging message based on the first SS/PBCH block,
based on the identification that the interval between the first time and the second time is greater than or equal to the specified value,
receive the paging message without receiving the first SS/PBCH block;
store the received paging message in the memory;
receive a second SS/PBCH block after receiving the paging message; and
process the stored paging message based on the second SS/PBCH block received after reception of the paging message.
|