| CPC H04L 25/03006 (2013.01) [H04L 25/025 (2013.01); H04L 2025/0349 (2013.01); H04L 2025/03636 (2013.01)] | 20 Claims |
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1. An interference cancellation circuit comprising:
a relative delay control circuit configured to receive a first transmission signal of a first frequency and a second transmission signal of a second frequency different from the first frequency, wherein the relative delay control circuit includes a first delay buffer that is configured to delay the second transmission signal by a first delay time and a second delay buffer that is configured to delay the second transmission signal by a second delay time;
a delay reference generation circuit configured to receive, from the relative delay control circuit, the first transmission signal and the delayed second transmission signal, and to generate reference signals corresponding to the first transmission signal and the delayed second transmission signal;
a weight control circuit configured to update a weight vector;
a relative delay estimation circuit configured to estimate a relative delay based on the reference signals; and
an adaptive filter configured to generate an interference model signal based on the weight vector and a first reference signal of the reference signals and filter the interference model signal.
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