US 12,375,087 B2
Clock management apparatus, clock frequency division module and system-on-chip
Yaqian He, Shanghai (CN); and Li Tong, Shanghai (CN)
Assigned to ESPRESSIF SYSTEMS (SHANGHAI) CO., LTD., Shanghai (CN)
Appl. No. 18/548,044
Filed by ESPRESSIF SYSTEMS (SHANGHAI) CO., LTD., Shanghai (CN)
PCT Filed Dec. 31, 2021, PCT No. PCT/CN2021/143716
§ 371(c)(1), (2) Date Aug. 25, 2023,
PCT Pub. No. WO2022/179309, PCT Pub. Date Sep. 1, 2022.
Claims priority of application No. 202110253009.3 (CN), filed on Feb. 25, 2021.
Prior Publication US 2024/0146310 A1, May 2, 2024
Int. Cl. H03L 7/00 (2006.01); G06F 1/08 (2006.01); G06F 1/12 (2006.01); H03K 3/037 (2006.01); H03K 5/22 (2006.01)
CPC H03L 7/00 (2013.01) [G06F 1/08 (2013.01); G06F 1/12 (2013.01); H03K 3/037 (2013.01); H03K 5/22 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A clock management apparatus, comprising a clock synchronization signal generator, a plurality of clock gating units, and a plurality of clock frequency division modules;
wherein the clock synchronization signal generator is configured to generate a synchronization signal of a predetermined period;
the plurality of clock gating units are in one-to-one correspondence with the plurality of clock frequency division modules, and each of the plurality of clock gating units is connected in series with a corresponding one of the plurality of clock frequency division modules to form a signal processing branch; a plurality of the signal processing branches are connected in parallel and configured to receive a source clock signal respectively; the clock gating unit is configured to control an on-off switch of the signal processing branch, and the clock frequency division module is configured to perform phase adjustment on a clock signal of the signal processing branch after receiving a synchronization signal output by the clock synchronization signal generator, to adjust clock signals of the plurality of signal processing branches from an asynchronous state to a synchronous state.