| CPC H02J 7/0014 (2013.01) [G01R 31/382 (2019.01); G01R 31/396 (2019.01); H02J 7/00036 (2020.01); H02J 7/0048 (2020.01); H02J 7/0071 (2020.01); H02J 50/12 (2016.02)] | 25 Claims |

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1. An apparatus comprising:
at least one memory;
instructions; and
processor circuitry configured to at least one of instantiate or execute the instructions to:
identify a first battery node to transmit an uplink command during a first superframe interval;
transmit a downlink command to the first battery node and a second battery node, the first battery node to switch in the first superframe interval from a receive state to a transmit state in response to the downlink command, the first battery node to transmit the uplink command in the transmit state; and
receive the uplink command from the first battery node in the first superframe interval.
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