US 12,374,624 B2
Semiconductor devices
Pei-Yu Wang, Hsinchu (TW); and Yu-Xuan Huang, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Apr. 11, 2024, as Appl. No. 18/633,002.
Application 18/633,002 is a continuation of application No. 17/870,531, filed on Jul. 21, 2022, granted, now 11,984,402.
Application 17/870,531 is a continuation of application No. 17/015,628, filed on Sep. 9, 2020, granted, now 11,410,930, issued on Aug. 9, 2022.
Claims priority of provisional application 63/016,505, filed on Apr. 28, 2020.
Prior Publication US 2024/0258237 A1, Aug. 1, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 23/528 (2006.01); H01L 21/02 (2006.01); H01L 21/285 (2006.01); H01L 21/311 (2006.01); H01L 29/06 (2006.01); H01L 29/417 (2006.01); H01L 29/423 (2006.01); H01L 29/45 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/786 (2006.01); H10D 30/01 (2025.01); H10D 30/67 (2025.01); H10D 30/69 (2025.01); H10D 62/00 (2025.01); H10D 62/10 (2025.01); H10D 64/01 (2025.01); H10D 64/62 (2025.01)
CPC H01L 23/5286 (2013.01) [H01L 21/02603 (2013.01); H01L 21/28518 (2013.01); H01L 21/31116 (2013.01); H01L 21/31144 (2013.01); H10D 30/031 (2025.01); H10D 30/6713 (2025.01); H10D 30/6729 (2025.01); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 30/797 (2025.01); H10D 62/021 (2025.01); H10D 62/121 (2025.01); H10D 64/017 (2025.01); H10D 64/018 (2025.01); H10D 64/62 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A device comprising:
a first nanostructure;
a gate structure wrapped around the first nanostructure;
a first source/drain region adjacent the gate structure;
a first dielectric layer over the first source/drain region;
an interlayer dielectric over the first dielectric layer, a material of the interlayer dielectric being different than a material of the first dielectric layer; and
a conductive line extending through the interlayer dielectric, the conductive line disposed over the first source/drain region, the conductive line isolated from the first source/drain region by the first dielectric layer, a top surface of the conductive line being coplanar with a top surface of the gate structure.