US 12,374,611 B2
Package core assembly and fabrication methods
Han-Wen Chen, Cupertino, CA (US); Steven Verhaverbeke, San Francisco, CA (US); Giback Park, San Jose, CA (US); Kyuil Cho, Santa Clara, CA (US); Kurtis Leschkies, San Jose, CA (US); Roman Gouk, San Jose, CA (US); Chintan Buch, Santa Clara, CA (US); Vincent Dicaprio, Pleasanton, CA (US); Bernhard Stonas, Hayward, CA (US); and Jean Delmas, Santa Clara, CA (US)
Assigned to Applied Materials, Inc., Santa Clara, CA (US)
Filed by Applied Materials, Inc., Santa Clara, CA (US)
Filed on Apr. 12, 2021, as Appl. No. 17/227,837.
Application 17/227,837 is a continuation of application No. 16/886,704, filed on May 28, 2020, granted, now 12,087,679.
Application 16/886,704 is a continuation in part of application No. 16/698,680, filed on Nov. 27, 2019, granted, now 11,862,546.
Prior Publication US 2021/0257289 A1, Aug. 19, 2021
Int. Cl. H01L 23/498 (2006.01); H01L 21/48 (2006.01); H01L 23/14 (2006.01)
CPC H01L 23/49838 (2013.01) [H01L 21/486 (2013.01); H01L 23/147 (2013.01); H01L 23/49827 (2013.01); H01L 23/49866 (2013.01)] 24 Claims
OG exemplary drawing
 
1. A semiconductor device assembly, comprising:
a silicon core structure, comprising:
a first side opposing a second side;
a first via comprising a first via surface that defines an opening extending through the silicon core structure from the first side to the second side; and
a first pocket formed in the silicon core structure, the first pocket comprising a first plurality of pocket walls that define a first opening in the silicon core structure;
a first conductive interconnection formed in the first via and having a surface exposed at the first side and the second side;
a capacitor disposed in the first pocket and coupled to a second conductive interconnection exposed at the first side or the second side; and
an insulating layer disposed over and in contact with the first side, the second side, the first via surface, and the first plurality of pocket walls, wherein a single material of the insulating layer surrounds all surfaces of the capacitor in the first opening defined by the first plurality of pocket walls and forming an intermediate layer between the first conductive interconnection and the first via surface, the insulating layer disposed within the opening of the first pocket and between a periphery of the capacitor and each of the first plurality of pocket walls, wherein all surfaces of the capacitor are in contact with the insulating layer and the insulating layer is the only insulating layer used to support the capacitor.