| CPC G11C 17/165 (2013.01) [B41J 2/04511 (2013.01); B41J 2/04541 (2013.01); B41J 2/0455 (2013.01); G11C 17/18 (2013.01); H10B 20/25 (2023.02)] | 20 Claims |
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1. A device comprising:
a plurality of units arrayed in a predetermined direction;
a first terminal configured to supply a voltage to the plurality of units; and
a second terminal configured to supply a voltage to the plurality of units,
wherein the plurality of units include:
a first unit including a memory element arranged between the first terminal and the second terminal, and a first transistor configured to perform write to the memory element, wherein the first transistor can be controlled to change between a conductive state and a non-conductive state by a voltage on a first signal line; and
a second unit including a second transistor arranged between the first terminal and the second terminal in correspondence with the first transistor of the first unit, wherein the second transistor can be controlled to change between a conductive state and a non-conductive state by a voltage on a second signal line,
wherein the voltage on the first signal line can be controlled independently of the voltage on the second signal line, a voltage on the first terminal, and a voltage on the second terminal, and
wherein the voltage on the second signal line can be controlled independently of the voltage on the first signal line, the voltage on the first terminal, and the voltage on the second terminal.
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