| CPC G09G 3/3266 (2013.01) [G09G 3/32 (2013.01); G09G 2300/0861 (2013.01); G09G 2310/0267 (2013.01); G09G 2310/08 (2013.01); G09G 2330/021 (2013.01)] | 20 Claims |
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1. A stage circuit for a display gate driver comprising:
an output unit connected to a first power input terminal to which a first power source is input and a second power input terminal to which a second power source is input, the output unit configured to output an enable output signal to a first output terminal, corresponding to a voltage of a second node;
a first driver connected to the first power input terminal, the second power input terminal, a clock input terminal configured to receive a clock signal, and a second input terminal configured to receive a previous enable output signal, the first driver being configured to control the voltages of a first node and the second node wherein the first driver outputs an enable carry signal at a first node to a second output terminal; and
a second driver connected to a first input terminal configured to receive a previous enable carry signal, the second input terminal, the first power input terminal, and the clock input terminal, the second driver being configured to control a voltage of the first node,
wherein the second driver includes:
a first transistor connected between the first node and the clock input terminal, the first transistor including a gate electrode connected to a control node; and
a control transistor and a first capacitor, connected in series between the control node and the clock input terminal, the control transistor including a gate electrode connected to the first input terminal.
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