US 12,373,676 B2
Techniques for accelerating neural networks
Gurpreet S Kalsi, Bangalore (IN); Ramachandra Chakenalli Nanjegowda, Bangalore (IN); Kamlesh R Pillai, Bangalore (IN); and Sreenivas Subramoney, Bangalore (IN)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Feb. 10, 2021, as Appl. No. 17/172,627.
Prior Publication US 2021/0166114 A1, Jun. 3, 2021
Int. Cl. G06N 3/063 (2023.01); G06F 17/16 (2006.01); G06N 3/04 (2023.01); G06N 3/0442 (2023.01); G06N 3/045 (2023.01)
CPC G06N 3/063 (2013.01) [G06F 17/16 (2013.01); G06N 3/04 (2013.01)] 18 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
interface circuitry;
a memory controller:
machine-readable instructions; and
at least one processor circuit to be programmed by the machine-readable instructions to:
generate a first output vector, the first output vector determined based on a gated current unit (GRU) step computation for a first layer of a neural network;
generate an output feature vector for a second layer of the neural network, wherein at least a portion of of the GRU step computation for the first layer overlaps at least a portion of a linear classifier (LC) step computation of the output feature vector for the second layer of the neural network; and
generate an activation vector based on the first output vector, the LC step computation based on the activation vector, the activation vector stored in a buffer by the memory controller between iterations of the GRU step computation or the LC step computation involving a GRU weight matrix or an LC weight matrix.